1. Field of the Invention
This invention relates generally to differential comparator circuits. More particularly, it relates to an improved architecture for differential comparator circuits having lower power requirements.
2. Background of Related Art
FIG. 1 shows one type conventional differential comparator circuit having hysteresis for differential AC coupled input signals.
In particular, in FIG. 1, a differential comparator circuit includes a negative input IN, a positive input IP, a negative output ON, and a positive output OP. The negative input IN and the positive input IP are AC coupled with capacitors 104 and 106, respectively.
The bias voltage for the comparator input stage is set in part by resistors 122 and 124 setting the reference point VSG. The input hysteresis is set by feeding the comparator output signal through the resistive voltage dividers built from resistors 110, 112 and 118, 120. Resistors 114 and 116 help reduce the AC loading of the input signal at the comparator inputs while coupling the reference point VSG bias voltage and hysteresis feedback signal to the comparator inputs.
A disadvantage of a conventional differential comparator circuit having hysteresis such as the one shown in FIG. 1 is that a large DC current flow is necessary to set the hysteresis and signal reference point. For instance, in a given example, resistor 110=6K, resistor 112=88K, resistor 114=100K, resistor 116=100K, resistor 118=88K, resistor 120=6K, resistor 122=30K, and resistor 124=30K. In this example, the differential comparator circuit as shown in FIG. 1 requires a total supply current of approximately 335 microamps (xcexcA), comprising approximately 225 xcexcA for the differential comparator 102 and its bias circuit, plus approximately 110 xcexcA necessary to provide the hysteresis and reference point voltage levels.
There is a need for an improved architecture for a differential comparator having hysteresis which utilizes less power than conventional comparator circuits.
In accordance with the principles of the present invention, a low power differential comparator circuit comprises a differential comparator. A positive feedback circuit is between a positive output node of the differential comparator and a positive input node to an input stage of the differential comparator. The positive feedback circuit includes a first switch. A positive feedback circuit is between a negative output node of the differential comparator and a negative input node to the input stage of the differential comparator. The positive feedback circuit includes a second switch. The first switch and the second switch operate mutually exclusively.
A method of providing hysteresis in a differential comparator comprises connecting and disconnecting positive feedback between output nodes of the differential comparator and input nodes to an input stage of the differential comparator.
A differential comparator having isolated hysteresis values in accordance with another aspect of the present invention comprises a comparator. A bias circuit biases an input stage of the comparator. The bias circuit includes at least one feedback transistor and a bias resistor. A differential output stage is connected to the comparator. Any change in a current flow through the bias resistor of the bias circuit is substantially compensated by a change in current flow through the at least one feedback transistor in the bias circuit.
A method of compensating a change in input stage bias to a differential comparator due to a variation in a power supply voltage in accordance with another aspect of the present invention comprises compensating any change in an output current from a bias resistor in a bias circuit to a differential comparator with a corresponding change in current in a feedback transistor connected to the bias resistor.